STM32F429NET6TR datasheet(124/231 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F427xx STM32F429xx

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DocID024030 Rev 6

IDD(PLLI2S)(4)

PLLI2S power consumption on

VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLI2S)(4)

PLLI2S power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

Table 44. PLLI2S (audio PLL) characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 45. PLLISAI (audio and LCD-TFT PLL) characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLLSAI_IN

PLLSAI input clock(1)

0.95(2)

12.10

MHz

fPLLSAI_OUT

PLLSAI multiplier output clock

216

MHz

fVCO_OUT

PLLSAI VCO output

100

432

MHz

tLOCK

PLLSAI lock time

VCO freq = 100 MHz

200

µs

VCO freq = 432 MHz

100

300

Jitter(3)

Main SAI clock jitter

Cycle to cycle at

12.288 MHz on

48KHz period,

N=432, R=5

RMS

peak

±280

Average frequency of

12.288 MHz

N = 432, R = 5

on 1000 samples

-90

FS clock jitter

Cycle to cycle at 48 KHz

on 1000 samples

-400

IDD(PLLSAI)(4)

PLLSAI power consumption on

VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLSAI)(4)

PLLSAI power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization results.

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