STM32F427NET6 datasheet(162/231 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F427xx STM32F429xx

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DocID024030 Rev 6

Figure 54. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

tSETTLING(4)

Settling time (full scale: for a

10-bit input code transition

between the lowest and the

highest input codes when

DAC_OUT reaches final

value ±4LSB

-3

µs

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

THD(4)

Total Harmonic Distortion

Buffer ON

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

Update

rate(2)

Max frequency for a correct

DAC_OUT change when

small variation in the input

code (from code i to i+1LSB)

MS/s

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

tWAKEUP(4)

Wakeup time from off state

(Setting the ENx bit in the

DAC Control register)

-6.5

µs

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

input code between lowest and highest

possible ones.

PSRR+ (2)

Power supply rejection ratio

(to VDDA) (static DC

measurement)

–67

–40

dB No RLOAD, CLOAD = 50 pF

1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:

Internal reset OFF).

2. Guaranteed by design.

3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic

consumption occurs.

4. Guaranteed by characterization.

Table 85. DAC characteristics (continued)

Symbol

Parameter

Min

Typ

Max

Unit

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