IP1001 LF
Data Sheet
9/48
Dec. 18, 2007
Copyright © 2006, IC Plus Corp.
IP1001-DS-R06
Pin no.
Label
Type
Description
MAC Interface
GMII
RGMII
MII
39
RX_CLK RXC
RX_CLK O
GMII/ RGMII Receive Clock.
I/F
MDI
speed
Description
Gigabit 125Mhz output.
IP1001 sends out RXD[7:0],
RXDV and RX_ER at the
rising edge of RX_CLK.
100Mbps 25Mhz output.
IP1001 sends out RXD[3:0],
RXDV and RX_ER at the
rising edge of RX_CLK.
GMII
Mode
10Mbps 2.5Mhz output.
IP1001 sends out RXD[3:0],
RXDV and RX_ER at the
rising edge of RX_CLK.
Gigabit 125Mhz output.
IP1001 sends out RXD[3:0]
and RX_CTL at both the
rising edge and falling edge
of RXC.
100Mbps 25Mhz output.
IP1001 sends out RXD[3:0]
and RX_CTL at both the
rising edge and falling edge
of RXC.
RGMII
Mode
10Mbps 2.5Mhz output.
IP1001 sends out RXD[3:0]
and RX_CTL at both the
rising edge and falling edge
of RXC.
40
RX_DV
RX_CTL RX_DV
O
GMII and MII Receive Enable/ RGMII Receive
Control
I/F
MDI
speed
Description
GMII
Mode
Gigabit
100Mbps
10Mbps
RX_DV indicates the valid
data is present on the data
bus of RXD. Synchronous to
the rising edge of RX_CLK.
Gigabit
100Mbps
RGMII
Mode
10Mbps
RX_CTL indicates a signal
like RX_DV at the rising edge
of TXC. A signal like RX_ER
is derived by the logical
operation of latched RX_DV
and the value at the falling
edge of RX_CLK
51,50,49,48 RXD[7:4] --
--
O
GMII Receive Data (high nibble)
Please see the pin description of pin 39.
RXD[7:4] share the same pins with
PHY_ADDR[3:4], TXPHASE_SEL, and
RXPHASE_SEL.
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