IP101A LF
Data Sheet
13/36
Oct 22, 2007
Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12
2
Register Descriptions
Bit
Name
Description/Usage
Default value
(h): 3100
Register 0 : MII Control Register
15
Reset
When set, this action will bring both status and control
registers of the PHY to default state. This bit is self-clearing.
1 = Software reset
0 = Normal operation
0, RW
14
Loop-back
This bit enables loop-back of transmit data to the receive
data path, i.e., TXD to RXD. IP101A LF requires at least
512us to link after programming this bit. TX/RX packets
should be activated after 512us.
1 = enable loop-back
0 = normal operation
0, RW
13
Speed Selection
This bit sets the speed of transmission.
1 = 100Mbps
0 = 10Mbps
1, RW
12
Auto-
Negotiation
Enable
This bit determines the auto-negotiation function.
1 = enable auto-negotiation; bits 13 and 8 will be ignored.
0 = disable auto-negotiation; bits 13 and 0:<8> will determine
the link speed and the data transfer mode, under this condition.
Auto-MDIX function should be disabled (set Reg16.11=1) if
this bit has been set to “0”. Please refer to section 7
Auto-MDIX function description for details.
1, RW (TP)
11
Power Down
This bit will turn down the power of the PHY chip and the
internal crystal oscillator circuit if this bit is enabled. The MDC
and MDIO are still activated for accessing to the MAC.
1 = power down
0 = normal operation
0, RW
10
Isolate
1=electrically Isolate PHY from MII but not isolate MDC and
MDIO
0=normal operation
0,RW
9
Restart Auto-
Negotiation
This bit allows the auto-negotiation function to be reset.
1 = restart auto-negotiation
0 = normal operation
0, RW
8
Duplex Mode
This bit sets the duplex mode if auto-negotiation is disabled (bit
12=0)
1 = full duplex
0 = half duplex
After completing auto-negotiation, this bit will reflect the
duplex status.(1: Full duplex, 0: Half duplex)
1, RW
7
Collision Test
1=enable COL signal test
0=disable COL signal test
0,RW
6:0
Reserved
0, RO
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