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IP101A LF
Data Sheet
7.2.2
RMII Timing
a.
Pin Reset and Clock output timing relationship
(If pin 16 has been configured as 50MHz output )
Symbol
Description
Min.
Typ.
Max.
Unit
Tdelay
Delay time after reset to clock output
-
40
-
us
C50M_O
T
delay
RESET_N
b. Clock Timing RMII
Symbol
Description
Notes
Min
Typ
Max
Units
TR_CLKRMII
REFCLK Rise time
VIL (max) to VIH (min)
-
-
3.0
ns
TF_CLKRMII
REFCLK Fall time
VIH (min) to VIL (max)
-
-
3.0
ns
TP_CLKRMII
REFCLK Period
20.0 ± 50
ppm
ns
TH_CLKRMII
REFCLK High
8.0
10.0
12.0
ns
TL_CLKRMII
REFCLK Low
8.0
10.0
12.0
ns
T P_CLKRMII
T H_CLKRMII
T L_CLKRMII
T R_CLKRMII
T F_CLKRMII
REFCLK
V IH
V IL
Figure 4: Clock Timing RMII
c.
RMII Receive Timing
Symbol
Description
Notes
Min
Typ
Max
Units
TDLY_RXD
REFCLK rising edge
to RXD[1:0], RX_ER
and CRS_DV delay
Initial rising edge of
CRS_DV is
asynchronous to
REFCLK
12.0
15.0
ns
TR_RXD
RXD[1:0], RX_ER,
CRS_DV Rise time
VIL (max) to VIH (min)
1.0
2.5
ns
TF_RXD
RXD[1:0], RX_ER,
CRS_DV Fall time
VIH (min) to VIL (max)
1.0
2.5
ns
Oct 22, 2007
33/36
Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12
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