IP101ALF-DS-R06 datasheet(27/36 Pages) ETC2

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IP101A LF

Data Sheet

27/36

Oct 22, 2007

IP101A LF-DS-R12

Power-Down Modes

IP101A LF can be power-down by 4 methods. These 4 methods are as follow:

Power Down in bit 11 of Register 0: Enable this bit will disconnect the power to IP101A LF and also

internal clock, but MDC and MDIO are still activated.

APS mode in bit 1 of Register 16: Set high to this bit will set PHY into power saving mode(APS sleeping

mode) while link is down, MDC and MDIO are kept activated. IP101A LF will send NLP every 64ms during

APS sleeping mode.

Analog off in bit 0 of Register 16: Enable this bit will put IP101A LF in analog off state. This will power

down all analog functions but internal 25MHz operating clock is active, and MDC and MDIO are also

activated.

ISOL pin (pin 43): Set high will isolate IP101A LF from MAC and disable management interface (MDC and

MDIO). The power usage is at minimum when this pin is activated.

Repeater Modes

To enter Repeater mode, one can either set pin 40 (RPTR) to high or set 1 to bit 2 of Register 16 will allow

IP101A LF to enter Repeater mode. If IP101A LF is used in repeater, CRS will be high if IC is in process of

receiving packets, while IP101A LF is used in a network interface card, CRS will be generated in both

transmitting and receiving packets.

Miscellaneous

ISET (pin 28) should be connected to GND via a 6.2k ohm resistor with 1% accuracy to ensure a correct

driving current for transmit DAC.

Set low to pin 42, REST_N, for at least 10ms will reset all functions available in IP101A LF. The bit 15 of

Interrupt

IP101A LF provides 4 kinds of interrupt function: speed change, duplex change, link change and arbiter

state change. Interrupt masks could be selected by Reg 17, and an active low interrupt will be sent from

pin48 when event occurs.

IP101ALF-DS-R06 数据表(PDF) 27 Page - List of Unclassifed Manufacturers