IP101A LF
Data Sheet
10/36
Oct 22, 2007
Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12
Pin Descriptions (continued)
Pin no.
Label
Type
Description
LED and PHY Address Configuration
These five pins are latched into the IP101A LF during reset to configure PHY address [4:0] used for MII
management register interface. And then, in normal operation after initial reset, they are used as driving
pins for status indication LED. The driving polarity, active low or active high, is determined by each
latched status of the PHY address [4:0] during reset. If latched status is high then it will be active low,
and if latched status is Low then it will be active high. Moreover, IP101A LF provides 2 LED operation
modes. If 2
nd LED mode is selected by pulling up pin CRS, only 4 LEDs are needed for status
indication. Default is first LED mode.
LED mode 1
LED mode 2
LED0
LINK
LINK /ACT(blinking)
LED1
FULL DUPLEX
FULL DUPLEX /COL(blinking)
LED2
10BT /ACT(blinking)
10BT
LED3
100BT /ACT(blinking)
100BT
LED4
COL
Reserved
9
PHYAD0/
LED0
LI/O
PHY Address [0]
Status:
Mode1: Active when linked.
Mode2: Active when linked and blinking when transmitting or
receiving data.
10
PHYAD1/
LED1
LI/O
PHY Address [1]
Status:
Mode1: Active when in Full Duplex operation.
Mode2: Active when in Full Duplex operation and blinking when
collisions occur.
12
PHYAD2/
LED2
LI/O
PHY Address [2]
Status:
Mode1: Active when linked in 10Base-T mode, and blinking
when transmitting or receiving data.
Mode2: Active when linked in 10Base-T mode.
13
PHYAD3/
LED3
LI/O
PHY Address [3]
Status:
Mode1: Active when linked in 100Base-TX and blinking when
transmitting or receiving data.
Mode2: Active when linked in 100Base-TX mode.
15
PHYAD4/
LED4
LI/O
PHY Address [4]
Status:
Mode1: Active when collisions occur.
Mode2: Reserved.
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
