IP101A LF
Data Sheet
30/36
Oct 22, 2007
Copyright © 2004, IC Plus Corp.
IP101A LF-DS-R12
6
Layout Guideline
General Layout Guideline
Best performance depends on good layout. The following recommendation steps will help customer to
gain maximum performance.
Create good power source to minimize noise from switching power source.
All components are qualified, especially high noise component, such as clock component.
Use bulk capacitors between power plane and ground plane for 4 layers board, signals trace on
component and bottom side, power plane on third layer, and ground layer on second layer.
Use decoupling capacitors to decouple high frequency noise between chip’s power and ground,
must be as close as possible to IP101A LF.
The clock trace length to IP101A LF must be equal the clock trace length to MAC.
Use guard traces to protect clock traces if possible
Avoid signals path parallel to clock signals path, because clock signals will interference with other
parallel signals, degrading signal quality, such as MDC and X1signals.
The clock must be low jitter with less than 0.5ns for 25/50/125Mhz 100ppm.
Avoid highly speed signal across ground gap to prevent large EMI effect.
Keep ground region as one continuous and unbroken plane.
Place a gap between the system and chassis grounds.
No any ground loop exists on the chassis ground.
Twisted Pair recommendation
When routing the TD+/- signal traces from IP101A LF to transformer, the traces should be as short as
possible, the termination resistors should be as close as possible to the output of the TD+/- pair of IP101A
LF. Center tap of primary winding of these transformers must be connected to analog 2.5V respectively. It
is recommended that RD+/- trace pair be route such that the space between it and others is three times
space, which can separate individual traces from one another.
It is recommended that offers chassis ground in the area between transformer and media connector
(RJ-45 port), this isolates the analog signals from external noise sources and reduces EMI effect. Note the
usage of the vias, it is best not use via to place anywhere other than in close proximity to device, in order
to minimize impedance variations in a given signal trace.
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