IP1000A LF
Preliminary Data Sheet
58/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
10
D2Support
D2 Power State Support. When D2Support is a
logic 1, the IP1000A LF supports the D2 power
state (see section 2.2.5.1).
D2Support is loaded from the ConfigParm field of an
EEPROM during auto initialization of the IP1000A
LF.
R
15..11 PmeSupport
Power Management Event Support. PmeSupport
indicates the power states from which the
IP1000A LF is able to generate a power
management event by asserting the PMEN signal.
Each bit
corresponds to a power state. A logic 1
in a particular bit position indicates that evens can
be generated from the indicated power state.
PmeSupport bits 14 and 11 are always set to a
logic 1 while bits 12, 13, and 15 are loaded from
the ConfigParm field of an EEPROM during auto
initialization of the IP1000A LF.
R
3.2.2.21 PowerMgmtCtrl
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x54
Default Value ................ 0x4000
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
1..0
PowerState
Power State. PowerState indicates the current
power state of the IP1000A LF. If PowerState is set
to a value other than 0x0, the IP1000A LF will not
respond to PCI I/O or memory cycles, nor will the
IP1000A LF be able to generate PCI bus master
cycles.
BIT 1
BIT 0
POWER STATE
0
0
D0
0
1
D1
1
0
D2
1
1
D3
R/W
7..2
Reserved
Reserved for future use. Write as zero, ignore on read.
N/A
8
PmeEn
Power Management Event Enable. When PmeEn
is a logic 1, the IP1000A LF is allowed to report
wake events on the PMEN signal. The criteria for
generating
wake
events
is
defined
by
the
WakeEvent register. PmeEn is loaded from the
ConfigParm field of an EEPROM during auto
initialization of the IP1000A LF.
R/W
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