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IP175A LF
Preliminary Data Sheet
12/60
February 20, 2006
Copyright © 2004, IC Plus Corp.
IP175A LF-DS-R08
Pin Descriptions (continued)
Pin no.
Label
Type
Description
External MII1 interface (PHY mode only, P4EXT=1)
62
MII1_TXCLK
O
MII Transmit clock
61, 60,
59, 58
TXD1_0, TXD1_1,
TXD1_2, TXD1_3
IPL2
MII transmit data
It is sampled at the rising edge of MII1_TXCLK.
57
TXEN1
IPL2
MII transmit enable
It is used to frame TXD1[3:0]. It is sampled at the rising edge of
MII1_TXCLK.
69
COL1
O
MII collision
It is active when PHY4 is set to be half duplex and a collision
event happens.
63
RXDV1
O
MII receive data valid
It is used to frame RXD1[3:0]. It is sent out at the falling edge of
MII1_RXCLK.
67, 66,
65, 64
RXD1_0, RXD1_1,
RXD1_2, RXD1_3
O
MII receive data
It is sent out at the falling edge of MII1_RXCLK.
68
MII1_RXCLK
O
MII receive clock
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