IP175A LF
Preliminary Data Sheet
50/60
February 20, 2006
Copyright © 2004, IC Plus Corp.
IP175A LF-DS-R08
Bit
Function
R/W
Description
Default
MII status register (address 01H)
2
Link Status
RO
LL
1 = Link Pass
0 = Link Fail
When read as logic 1, indicates that IP175A LF has
determined a valid link has been established. When read as
logic 0, indicates the link is not valid. This bit is cleared until
a valid link has been established and before reading the
contents of this registers.
0
1
Jabber Detect
1 = jabber condition detected
0 = no jabber condition detected
When read as logic 1, indicates that IP175A LF has detected
a jabber condition. This bit is always 0 for 100Mbps
operation and is cleared after IP113A reset. This bit is set
until jabber condition is cleared and reading the contents of
the register.
0
0
Extended
capability
RO
1 = Extended register capabilities
0 = No extended register capabilities
IP175A LF has extended register capabilities.
1
Bit
Function
R/W
Description
Default
PHY Identifier (address 02H)
15:0 PHY identifier
RO
IP175A LF OUI (Organizationally Unique Identifier) ID, the
msb is 3
rd bit of IP175A LF OUI ID, and the lsb is 18th bit of
IP175A LF OUI ID. IP175A LF OUI is 0090C3.
0243h
Bit
Function
R/W
Description
Default
PHY Identifier (address 03H)
15:10 PHY identifier
RO
IP175A LF OUI ID, the msb is 19
th bit of IP175A LF OUI ID,
and lsb is 24
th bit of IP175A LF OUI ID.
3h
9:4
Manufacture’s
Model Number
RO
IP175A LF model number
05h
3:0
Revision Number
RO
IP175A LF revision number
0
Bit
Function
R/W
Description
Default
Auto-Negotiation Advertisement register (address 04H)
15
Next Page
Not supported
0
14
Reserved
RW
Reserved by IEEE, write as 0, ignore on read
0
13
Remote Fault
R/W
Not supported
0
12:11 Reserved
RO
Reserved for future IEEE use, write as 0, ignore on read
0
10
Pause
RW
1 = Advertises that this device has implemented pause function
0 = No pause function supported
0
9
100BASE-T4
RW
Not supported
0
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