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IP175A LF
Preliminary Data Sheet
5.3
AC Timing
5.3.1
Reset Timing
Description
Min.
Typ.
Max.
Unit
X1 valid period before reset released
10
-
-
ms
Reset period
10
-
-
ms
MII clock comes out period after
reset released
-
1
-
µs
VCC
Power on
OSCI (X1)
resetb
Reset period
MII clock
Reset released
MII clock comes out period after reset released
X1 valid period before reset released
5.3.2
MII0 PHY Mode Timing
a. Transmit Timing Requirements
Symbol
Description
Min.
Typ.
Max.
Unit
TTxClk
Transmit clock period 100M MII
-
40
-
ns
TTxClk
Transmit clock period 10M MII
-
400
-
ns
TsTxClk
TXEN0, TXD0 to MII0_TXCLK setup time
2
-
-
ns
ThTxClk
TXEN0, TXD0 to MII0_TXCLK hold time
0.5
-
-
ns
M II0 _ T X C L K
TX E N 0 ,
TX D 0 [3 :0 ]
T sTxClk
T hTxClk
T TxClk
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February 20, 2006
Copyright © 2004, IC Plus Corp.
IP175A LF-DS-R08