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IP175ALF-DS-R03 数据表(PDF) 56 Page - List of Unclassifed Manufacturers

部件名 IP175ALF-DS-R03
功能描述  5 Port 10/100 Ethernet Integrated Switch
PDF  60 Pages
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制造商  ETC2 [List of Unclassifed Manufacturers]
网页  
标志 ETC2 - List of Unclassifed Manufacturers

IP175ALF-DS-R03 数据表(HTML) 56 Page - List of Unclassifed Manufacturers

Back Button IP175ALF-DS-R03 Datasheet HTML 52Page - List of Unclassifed Manufacturers IP175ALF-DS-R03 Datasheet HTML 53Page - List of Unclassifed Manufacturers IP175ALF-DS-R03 Datasheet HTML 54Page - List of Unclassifed Manufacturers IP175ALF-DS-R03 Datasheet HTML 55Page - List of Unclassifed Manufacturers IP175ALF-DS-R03 Datasheet HTML 56Page - List of Unclassifed Manufacturers IP175ALF-DS-R03 Datasheet HTML 57Page - List of Unclassifed Manufacturers IP175ALF-DS-R03 Datasheet HTML 58Page - List of Unclassifed Manufacturers IP175ALF-DS-R03 Datasheet HTML 59Page - List of Unclassifed Manufacturers IP175ALF-DS-R03 Datasheet HTML 60Page - List of Unclassifed Manufacturers  
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IP175A LF
Preliminary Data Sheet
5.3.3
MII1 PHY Mode Timing
a. Transmit Timing Requirements
Symbol
Description
Min.
Typ.
Max.
Unit
TTxClk
Transmit clock period 100M MII
-
40
-
ns
TTxClk
Transmit clock period 10M MII
-
400
-
ns
TsTxClk
TXEN, TXD to MII1_TXCLK setup time
2
-
-
ns
ThTxClk
TXEN, TXD to MII1_TXCLK hold time
0.5
-
-
ns
M II1 _ T X C L K
TX E N 1 ,
TX D 1 [3 :0 ]
T sTxClk
T hTxClk
T TxClk
b. Receive Timing
Symbol
Description
Min.
Typ.
Max.
Unit
TRxClk
Receive clock period 100M MII
-
40
-
ns
TRxClk
Receive clock period 10M MII
-
400
-
ns
TdRxClk
MII1_RXCLK falling edge to RXDV1, RXD1
1
-
4
ns
TdRxClk
MII1_RXCLK
RXDV1,
RXD1[3:0]
TRxClk
56/60
February 20, 2006
Copyright © 2004, IC Plus Corp.
IP175A LF-DS-R08



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