IP175A LF
Preliminary Data Sheet
46/60
February 20, 2006
Copyright © 2004, IC Plus Corp.
IP175A LF-DS-R08
ROM
MII
Pin name
Description
Default
EEPROM registers 17H
17[4:0] 17[10:6]
--
Remove VLAN tag
17H[0]
1: port0 removes the VLAN tag from each outgoing packet.
0: port0 doesn’t remove the VLAN tag.
17H[1]
1: port1 removes the VLAN tag from each outgoing packet.
0: port1 doesn’t remove the VLAN tag.
17H[2]
1: port2 removes the VLAN tag from each outgoing packet.
0: port2 doesn’t remove the VLAN tag.
17H[3]
1: port3 removes the VLAN tag from each outgoing packet.
0: port3 doesn’t remove the VLAN tag.
17H[4]
1: port4 removes the VLAN tag from each outgoing packet.
0: port4 doesn’t remove the VLAN tag.
5’b0
ROM
MII
Pin name
Description
Default
EEPROM registers 18H~21H
18[7:0] 18[7:0]
--
Vlan_tag_0_low
This register defines the low byte of VLAN tag for port 0.
(i.e. Port 0 vlan_tag[7:0])
8’b0
19[7:0] 18[15:8]
--
Vlan_tag_0_high
This register defines the high byte of VLAN tag for port 0.
(i.e. Port 0 vlan_tag[15:8])
8’b0
1A[7:0] 19[7:0]
--
Vlan_tag_1_low
This register defines the low byte of VLAN tag for port 1.
(i.e. Port 1 vlan_tag[7:0])
8’b0
1B[7:0] 19[15:8]
--
Vlan_tag_1_high
This register defines the high byte of VLAN tag for port 1.
(i.e. Port 1 vlan_tag[15:8])
8’b0
1C[7:0] 1A[7:0]
--
Vlan_tag_2_low
This register defines the low byte of VLAN tag for port 2.
(i.e. Port 2 vlan_tag[7:0])
8’b0
1D[7:0] 1A[15:8]
--
Vlan_tag_2_high
This register defines the high byte of VLAN tag for port 2.
(i.e. Port 2 vlan_tag[15:8])
8’b0
1E[7:0] 1B[7:0]
--
Vlan_tag_3_low
This register defines the low byte of VLAN tag for port 3.
(i.e. Port 3 vlan_tag[7:0])
8’b0
1F[7:0] 1B[15:8]
--
Vlan_tag_3_high
This register defines the high byte of VLAN tag for port 3.
(i.e. Port 3 vlan_tag[15:8])
8’b0
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