IP1000A LF
Preliminary Data Sheet
16/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
2.2.5.1
Power Management States
The IP1000A LF supports several power management states. The PowerState field in the
PowerMgmtCtrl register determines IP1000A LF’s current power state. The power states are defined as
follows:
D0 Uninitialized (power state 0) is entered as a result of hardware reset, or after a transition from D3
Hot to D0. This state is the same as D0 Active except that the PCI configuration registers are
uninitialized. In this state, the IP1000A LF responds to PCI configuration cycles only.
D0 Active (power state 0) is the normal operational power state for the IP1000A LF. In this state, the
PCI configuration registers have been initialized by the system, including the IoSpace,
MemorySpace, and BusMaster bits in the ConfigCommand register, so the IP1000A LF is able to
respond to PCI I/O, memory and configuration cycles and can operate as a PCI master. The
IP1000A LF cannot signal wake (PMEN on the PCI bus) from the D0 state.
D1 (power state 1) is a “light-sleep” state. The IP1000A LF optionally supports this state determined
by the D1Support bit in the ConfigParm word in the EEPROM. The D1 state allows transition back to
D0 with no delay. In this state, the IP1000A LF responds to PCI configuration accesses, to allow the
system to change the power state. The IP1000A LF’s function in the D1 state is to recognize wake
events and link state events and pass them on to the system by asserting the PMEN signal on the
PCI bus.
D2 (power state 2) is a partial power-down state. The IP1000A LF optionally supports this state
determined by the D2Support bit in the ConfigParm word in the EEPROM. D2 allows a faster
transition back to D0 than is possible from the D3 state. In this state, the IP1000A LF responds to
PCI configuration accesses, to allow the system to change the power state. In D2 the IP1000A LF
does not respond to any PCI I/O or memory accesses. The IP1000A LF’s function in the D2 state is
to recognize wake events and link state events and pass them on to the system by asserting the
PMEN signal on the PCI bus.
D3 Hot (power state 3) is the full power-down state for the IP1000A LF. In this state, the IP1000A LF
responds to PCI configuration accesses, to allow the system to change the power state back to D0
Uninitialized. In D3 hot, the IP1000A LF does not respond to any PCI I/O or memory accesses. The
IP1000A LF’s main responsibility in the D3 Hot state is to recognize wake events and link state
events and signal those to the system by asserting the PMEN signal on the PCI bus.
D3 Cold (power state undefined) is the power-off state for the IP1000A LF. The IP1000A LF does not
function in this state. When power is restored, the system guarantees the assertion of hardware
reset, which puts the IP1000A LF into the D0 Uninitialized state.
2.2.6
Wake On LAN
Wake on LAN is a key component of the IBM/Intel® Advanced Manageability Alliance (AMA) initiative.
The IP1000A LF implements a portion of the Wake On LAN functionality defined by the AMA initiative.
Specifically, the IP1000A LF can be configured to respond to wake up frames sent by a Wake On LAN
managerment station.
2.2.6.1
Wake Events
The IP1000A LF can generate wake events to the system as a result of Wake Packet reception, Magic
Packet reception, or due to a change in the link status. The WakeEvent register gives the host system
control over which of these events are passed to the system. Wake events are signaled over the PCI bus
using the PMEN signal.
A Wake Packet event is controlled by the WakePktEnable bit in WakeEvent register. The WakePktEnable
bit has no effect when IP1000A LF is in the D0 power state, as the wake process can only take place in
states D1, D2, or D3. When the IP1000A LF detects a Wake Packet, it signals a wake event on PMEN (if
PMEN assertion is enabled), and sets the WakePktEvent bit in the WakeEvent register. The IP1000A LF
can signal that a wake event has occurred when it receives a pre-defined frame from another station.
The host system transfers a set of frame data patterns into the transmit FIFO using the TxDMA function
before placing the IP1000A LF in a power-down state. Once powered down, the IP1000A LF compares
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