IP1000A LF
Preliminary Data Sheet
51/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
terminated with Split Response observes PERRN
asserted three clocks after the data phase.
The target (requester) of a Split Completion
calculates a data parity error in either read data or
a
Split
Completion
Message.
The
target
(requester) receives a Split Completion Message
that indicates a data parity error occurred on one
of this device’s non-posted write transactions.
10..9
DevselTiming
Device Select Timing. DevselTiming is used to
encode the slowest time with which the IP1000A
LF asserts the DEVSELN signal. A value of 0x1
for DevselTiming indicates support for “medium”
speed DEVSELN assertion.
R
11
SignaledTarget-
Abort
Signaled Target Abort. The IP1000A LF sets
SignaledTargetAbort to a logic 1 when the
IP1000A LF terminates a bus transaction with
target-abort.
R
12
ReceivedTarget-
Abort
Received Target Abort. The IP1000A LF sets
ReceivedTargetAbort to a logic 1 when, operating
as a bus master, an IP1000A LF bus transaction is
terminated with target-abort.
R
13
ReceivedMaster-
Abort
Received Master Abort. The IP1000A LF sets
ReceivedMasterAbort to a logic 1 when, operating
as a bus master, an IP1000A LF bus transaction is
terminated with master-abort.
R
14
SignaledSystem-
Error
Signaled
System
Error.
When
SignaledSystemError is a logic 1, the IP1000A LF
asserts the SERRN signal.
R
15
DetectedParity-
Error
Detected Parity Error. When DetectedParityError
is a logic 1 the IP1000A LF has detected a parity
error, regardless of whether parity error handling
is enabled.
R
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