TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

15

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are

summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions

of these registers are given in Table 3.

Table 3. Summary of Accessible Registers

REGISTER ADDRESS

O DLAB = 0

O DLAB = 0

1 DLAB = 0

2

3

4

5

6

7

O DLAB = 1

1 DLAB = 1

Bit

Receiver

Transmitter

Interrupt

Bit

No.

Buffer

Holding

Interrupt

p

Ident.

Line

Modem

Line

Modem

Scratch

Divisor

Latch

No.

Register

g

Register

p

Enable

Register

Control

Control

Status

Status

Scratch

Register

Latch

Latch

(MSB)

(Read

(Write

Register

(Read

Register

Register

Register

Register

Register

(LSB)

(MSB)

Only)

Only)

Only)

RBR

THR

IER

IIR

LCR

MCR

LSR

MSR

SCR

DLL

DLM

†

Enable

Word

†

Enable

Received

“0” If

Word

Length

Data

Data

Delta

0

Data Bit 0†

Data Bit 0

ece ed

Data

“0” If

Interrupt

Length

Select

Terminal

Data

Ready

Clear

Bit 0

Bit 0

Bit 8

0

Data Bit 0†

Data Bit 0

Available

Interrupt

Pending

Select

Bit 0

Ready

Ready

(DR)

to Send

Bit 0

Bit 0

Bit 8

Interrupt

Pending

Bit 0

(WLSO)

(DTR)

(DR)

(DCTS)

(ERBF)

(WLSO)

Enable

Enable

Transmitter

Word

Delta

as

e

Holding

Interrupt

Length

Request

Overrun

Data

1

Data Bit 1

Data Bit 1

g

Register

ID

g

Select

q

to Send

Error

Set

Bit 1

Bit 1

Bit 9

g

Empty

Bit (0)

Bit 1

(RTS)

(OE)

Ready

Interrupt

(WLS1)

(DDSR)

(ETBE)

Enable

Trailing

Receiver

Interrupt

Number of

Parity

Trailing

Edge Ring

2

Data Bit 2

Data Bit 2

Line Status

ID

Stop Bits

Out 1

y

Error

Edge Ring

Indicator

Bit 2

Bit 2

Bit 10

Interrupt

Bit (1)

(STB)

(PE)

Indicator

(TERI)

(ELSI)

(TERI)

Enable

Delta

Enable

Modem

Parity

Out 2

Framing

Receive

Li

3

Data Bit 3

Data Bit 3

ode

Status

0

Parity

Enable

Out 2

(Interrupt

Framing

Error

Line

Signal

Bit 3

Bit 3

Bit 11

Interrupt

(EDSSI)

(PEN)

Enable)

(FE)

Signal

Detect

(EDSSI)

Detect

(DRLSD)

Even

Bk

Clear

4

Data Bit 4

Data Bit 4

0

0

Even

Parity

Loop

Break

Interrupt

Clear

to

Bit 4

Bit 4

Bit 12

4

Data Bit 4

Data Bit 4

0

0

y

Select

Loop

Interrupt

(BI)

Send

Bit 4

Bit 4

Bit 12

(EPS)

(BI)

(CTS)

Transmit-

Data

5

Data Bit 5

Data Bit 5

0

0

Stick

0

ter

Holding

Data

Set

Bit 5

Bit 5

Bit 13

5

Data Bit 5

Data Bit 5

0

0

Parity

0

Holding

Register

Ready

(DSR)

Bit 5

Bit 5

Bit 13

g

(THRE)

(DSR)

S

Transmit-

ter

Ring

6

Data Bit 6

Data Bit 6

0

0

Set

Break

0

ter

Empty

Ring

Indicator

(RI)

Bit 6

Bit 6

Bit 14

Break

y

(TEMT)

(RI)

Divisor

Receive

7

Data Bit 7

Data Bit 7

0

0

Latch

Access

0

0

Line

Signal

Bit 7

Bit 7

Bit 15

7

Data Bit 7

Data Bit 7

0

0

Access

Bit

0

0

Signal

Detect

Bit 7

Bit 7

Bit 15

(DLAB)

(RLSD)

† Bit 0 is the least significant bit. It is the first bit serially transmitted or received.