TL16C451FN datasheet(20/24 Pages) TI

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

modem control register (MCR) (continued)

D Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When this bit is set, the

following occurs:

The SOUT is asserted high.

The SIN is disconnected.

The output of the transmitter shift register is looped back into the receiver shift register input.

The four modem status inputs (CTS, DSR, RLSD, and RI) are disconnected.

The MCR bits (DTR, RTS, OUT1, and OUT2) are connected to the modem status register bits (DSR,

CTS, RI, and RLSD), respectively.

The four modem control output terminals are forced to their inactive states (high).

In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify

the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.

The modem control interrupts are also operational but the modem control interrupt sources are now the

lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the

IER.

D Bits 5 through 7: These bits are always cleared.

modem status register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the

modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change

information; when a control input from the modem changes state the appropriate bit is set. All four bits are

cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are

described in the following bulleted list.

D Bit 0. This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input has changed

states since the last time it was read by the CPU. When this bit is set and the modem status Interrupt is

enabled, a modem status interrupt is generated.

D Bit 1. This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the DSR input has changed

states since the last time it was read by the CPU. When this bit is set and the modem status Interrupt is

enabled, a modem status interrupt is generated.

D Bit 2. This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip

has changed from a low to a high state. When this bit is set and the modem status Interrupt is enabled, a

modem status interrupt is generated.

D Bit 3. This bit is the delta receive line signal detect (DRLSD) indicator. Bit 3 indicates that the RLSD input

to the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem

status interrupt is enabled, a modem status interrupt is generated.

D Bit 4. This bit is the complement of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, bit

4 is equivalent to the MCR bit 1 (RTS).

D Bit 5. This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, bit

5 is equivalent to the MCR bit 0 (DTR).

D Bit 6. This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6

is equivalent to the MCR bit 2 (OUT 1).

D Bit 7. This bit is the complement of the receive line signal detect (RLSD) input. When bit 4 (loop) of the MCR

is set, bit 7 is equivalent to the MCR bit 3 (OUT 2).

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