TL16C451FN datasheet(19/24 Pages) TI

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

line status register (LSR)†

The LSR provides information to the CPU concerning the status of data transfers. The contents of this register

are summarized in Table 3 and are described in the following bulleted list.

D Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming

character has been received and transferred into the RBR and is cleared by reading the RBR.

D Bit 1‡: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character

in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator

is cleared every time the CPU reads the contents of the LSR.

D Bit 2‡: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received

data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the

CPU reads the contents of the LSR.

D Bit 3‡: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character

did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.

D Bit 4‡: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input

was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the

total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents

of the LSR.

D Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready

to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is

generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This

bit is cleared concurrent with the loading of the THR by the CPU.

D Bit 6: This bit is the transmitter empty (TEMT) indicator, bit 6 is set when the THR and the transmitter shift

TEMT bit is cleared.

D Bit 7: This bit is always clear.

† The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

‡ Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

modem control register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is

emulating a modem. The contents of this register are summarized in Table 3 and are described in the following

bulleted list.

D Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to

its active state (low). When bit 0 is cleared, DTR goes high.

D Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over

the DTR output.

D Bit 2: This bit (OUT 1) is a reserved location used only in the loopback mode.

D Bit 3: This bit (OUT 2) controls the output enable for the interrupt signal. When set, the interrupt is enabled.

When bit 3 is cleared, the interrupt is disabled.

TL16C451FN 数据表(PDF) 19 Page - Texas Instruments

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