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PIC16LF18323 数据表(PDF) 8 Page - Microchip Technology |
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PIC16LF18323 数据表(HTML) 8 Page - Microchip Technology |
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8 / 489 page  RC3 7 4 ANC3 — C1IN3- C2IN3- —— MDMIN(1) — CCP2(1) —— — — CLCIN1(1) — IOC Y — RC4 6 3 ANC4 — — — — — — — — — — — — — IOC Y — RC5 5 2 ANC5 — — — — MDCIN2(1) — CCP1(1) —— — —— — IOC Y — RC6 8 5 ANC6 — — — — — — — — — SS1(1) — — — IOC Y — RC7 9 6 ANC7 — — — — — — — — — — — — — IOC Y — VDD 1 18 — — — — — — — — — — — — — — — — VDD VSS 20 17 — — — — — — — — — — — — — — — — VSS OUT(2) — — — — C1OUT NCO1 — DSM TMR0 CCP1 PWM5 CWG1A CWG2A SDO1 DT CLC1OUT CLKR — — — — — — — C2OUT — — — — CCP2 PWM6 CWG1B CWG2B SCK1 CK CLC2OUT — — — — — — — — — — — — — CCP3 — CWG1C CWG2C SCL1(3) TX CLC3OUT — — — — — — — — — — — — — CCP4 — CWG1D CWG2D SDA1(3) —CLC4OUT — — — — TABLE 2: 20-PIN ALLOCATION TABLE (PIC16(L)F18344) (CONTINUED) Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 4: These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. |
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