ADS7828

15

SBAS181C

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LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS7828 circuitry. The basic SAR

architecture is sensitive to glitches or sudden changes on the

power supply, reference, ground connections, and digital

inputs that occur just prior to latching the output of the analog

comparator. Therefore, during any single conversion for an

“n-bit” SAR converter, there are n “windows” in which large

external transient voltages can easily affect the conversion

result. Such glitches might originate from switching power

supplies, nearby digital logic, and high-power devices.

With this in mind, power to the ADS7828 should be clean and

well-bypassed. A 0.1

µF ceramic bypass capacitor should be

placed as close to the device as possible. A 1

µF to 10µF

capacitor may also be needed if the impedance of the

connection between +VDD and the power supply is high.

The ADS7828 architecture offers no inherent rejection of

noise or voltage variation in regards to using an external

reference input. This is of particular concern when the

reference input is tied to the power supply. Any noise and

ripple from the supply will appear directly in the digital results.

While high-frequency noise can be filtered out, voltage varia-

tion due to line frequency (50Hz or 60Hz) can be difficult to

remove.

The GND pin should be connected to a clean ground point.

In many cases, this will be the “analog” ground. Avoid

connections that are too near the grounding point of a

microcontroller or digital signal processor. The ideal layout

will include an analog ground plane dedicated to the con-

verter and associated analog circuitry.