LP8552 datasheet(40/49 Pages) TI2

40 / 49 page

MCU

LP8552

VLDO

GNDs

ISET

VDDIO

PWM

SCLK

SDA

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

2.7V ± 22V

FILTER

+5V input rail

FSET

15 éH

VSYNC

COUT

CIN

10 éF

4.7 éF

CVLDO

1 éF

VDDIO reference voltage

VSYNC signal

120 k

100 nF

RISET

1 éF

FAULT

Can be left floating

if not used

39 pF

VIN

RFSET

VBATT 5.5V ± 22V

10 ± 40V, 180 ± 400 mA

10 ± 25V, 180 mA

LP8552

SNVS693E – SEPTEMBER 2011 – REVISED SEPTEMBER 2014

www.ti.com

Figure 32. Typical Application For Three Channels and Low Input Voltage

9.2.3.1 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range, VBATT

2.7 V to VOUT

5-V input rail, VLDO/VIN

4.5 V to 5.5 V, 10 mA

Brightness Control

PWM input duty cycle (default), I2C can be used as well

PWM output frequency

With RFSET resistor 85 kΩ to100 kΩ; 9.8 kHz with PSPWM enabled

LED Current

With RISET resistor 15 kΩ; 50 mA/LED string

Brightness slopes

200-ms linear slope + advanced slope

External set resistors

Enabled

Inductor

10 µH to 33 µH, with 2.5-A saturation current

Boost SW frequency

625 kHz

SW current limit

2.5 A

9.2.3.2 Detailed Design Procedure

Component selection follows Design Requirements above. VLDO capacitor voltage rating can be set based on the

5-V rail voltage specification, which must be < 5.5 V in all cases. Note that UVLO is detected from the VIN pin

voltage, not from the VBATT voltage.

9.2.3.3 Application Curves

Typical Boost and LED driver behavior is seen in the Application Curves section.

10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.7 V and 22 V. This input supply

should be well-regulated and able to withstand maximum input current and maintain stable voltage without

voltage drop even at load transition condition (start-up or rapid brightness change). The resistance of the input

supply rail should be low enough that the input current transient does not cause drop high enough in the LP8552

supply voltage that can cause false UVLO fault triggering.

Submit Documentation Feedback

Product Folder Links: LP8552

LP8552 数据表(PDF) 40 Page - Texas Instruments

LP8552 数据表(HTML) 40 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

数据表下载