LP8552 datasheet(12/49 Pages) TI2

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BOOST

LED

DRIVERS

LOGIC

EEPROM

C /

INTERFACE

LDO

OSC

TSD

PWM

DETECTOR

VLDO

GND

GND_SW

GND_LED

PWM

VDDIO

SCLK

SDA

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

PLL

FAULT

VIN

TEMP

SENSOR

MCU

VIN

FILTER

VSYNC

ISET

FSET

RISET

RFSET

LP8552

SNVS693E – SEPTEMBER 2011 – REVISED SEPTEMBER 2014

www.ti.com

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Clock Generation

The LP8552 has an internal 5-MHz oscillator which is used for clocking the boost converter, state machine, PWM

input duty cycle measurement, internal timings such as slope time for output brightness changes.

The internal clock can be used for generating the PWM output frequency. In this case the 5-MHz clock can be

multiplied with the internal PLL to achieve higher resolution. The higher the clock frequency for PWM generation

block, the higher the resolution; however, the tradeoff is higher IQ of the part. Clock multiplication is set with

<PWM_RESOLUTION[1:0]> EEPROM Bits.

The PLL can also be used for generating the required PWM generation clock from the VSYNC signal. This

makes sure that the LED output PWM is always synchronized to the VSYNC signal and there is no clock variation

between LCD display video update and the LED backlight output frequency. Also HSYNC signal up to 55 kHz can

be used.

PLL has an internal counter which has 13-bit control <PLL[12:0]> to achieve correct output clock frequency

based on the VSYNC frequency.

For the PLL it can take couple of seconds to synchronize the VSYNC signal to 60 Hz in start-up before the

correct PWM clock frequency is generated from internal oscillator. FILTER pin component selection affects the

time it takes from the PLL to lock to VSYNC signal.

Special logic is implemented for allowing steady clock frequency even if there are missing VSYNC pulses. In case

pulses are randomly left out, the LP8552 can generate the pulses internally while keeping the same PWM output

frequency. When VSYNC pulses are available again, the internal logic will automatically switch to the external

VSYNC clock without glitch.

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