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STM1831 数据表(PDF) 6 Page - STMicroelectronics

部件名 STM1831
功能描述  Voltage detector with sense input and external delay capacitor
PDF  24 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM1831 数据表(HTML) 6 Page - STMicroelectronics

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Description
STM1831
6/24
Doc ID 18180 Rev 1
1.1
Pin descriptions
See Figure 1 and Table 1 for a brief overview of the signals available on this device.
Power supply (VCC)
This pin is used to provide power to the device. A 0.1 µF decoupling ceramic capacitor is
recommended to be connected between the VCC and VSS pins, as close to the STM1831
device as possible.
Sense voltage input (VSEN)
Input voltage on this pin is monitored. When it drops below the threshold (VDET), reset
output (RST) is asserted. If VCC is close to 0 V, internal logic disconnects the voltage divider
from VSEN input in order to minimize ISEN current (see Figure 3 and Figure 20).
Reset output (RST)
Reset output is asserted when the voltage on the VSEN input pin drops below the threshold
(VDET).
The STM1831 has an open drain, active-low output which sinks current when the output is
asserted. Connect a pull-up resistor from RST to any supply voltage up to 6 V (see
Figure 4). Select a resistor value large enough to register a logic low, and small enough to
register a logic high, while all of the input current and leakage paths connected to the reset
output line are being supplied. A 10 k
Ω pull-up is sufficient in most applications.
The advantages of open drain output include the ability to connect more open drain outputs
in parallel (wired OR connections) as well as connecting the output to a power supply
voltage other than VCC.
Delay capacitor (CD)
Capacitor CD determines the delay (tCD) between reset deassertion and the moment when
VSEN voltage exceeds the VDET threshold (see Figure 5 with calculations for more details).
Any external leakage due to poor quality timing capacitors or excessive humidity may cause
a significant leakage current which extends the tCD timing. To minimize this effect, the PCB
tracks between the CD pin and its respective timing capacitor should be as short as
possible, properly covered with solder mask and isolated from other tracks (especially VSS)
by as great a distance as possible. Low-leakage timing capacitors (ceramic or film capacitor)
should be used.
Leave CD pin open if unused (i.e. tCD = 0 ms).



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