Operation

STM1831

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Doc ID 18180 Rev 1

2

Operation

The STM1831 voltage detector monitors system voltages from 1.6 V to 5.7 V in 100 mV

increments, has a voltage hysteresis (VHYS) and an output delay programmable by external

capacitor CD.

The STM1831 asserts a reset output (RST) whenever VCC goes below the detect voltage

(VDET). The reset output stays asserted until VCC goes above the detect voltage with

hysteresis (VDET + VHYS). If the external capacitor is connected to the CD pin, the reset

output deassertion is adequately delayed (see Figure 5 with calculations below for more

details). Leave the CD pin open if unused (i.e. tCD = 0 ms).

Figure 5.

Timing waveforms

tDET

detect delay time

tREL

release delay time (measured when external capacitor CD is disconnected)

tCD

delay by external capacitor CD.

The tCD delay can be calculated based on Equation 1:

Equation 1

and considering RCD = 2 MΩ (typ.) and VTCD = 1.5 V (typ.) at VCC = 3.0 V:

Equation 2

VSEN

CD

VDET

VDET + VHYST

RST

VTCD

tREL + tCD

tDET

AM00854

t

CD

R

–

CD

C

D

In 1

V

TCD

V

CC

--------------

–

⎝⎠

⎛⎞

×

×

=

t

CD

1.39

10

6

C

D

×

×

sF

,

()

≅