5V

B1

B2

A1

A2

GND

LSF0002

RA1 =

1k

RA2 =

1k

1.2V Device

1.2 ± 10% V

VBIAS

0.1 F

RB1 =

1k

RB2 =

1k

6

5

2

1

3

4

VEXT,A

VEXT,B

SW

SW

GPIO

3.3V

GPIO

GPIO

GPIO

Figure 8-3. Multi-Voltage Translation Example with the LSF Translators

8.2.3 Voltage Translation for Vref_B < Vref_A + 0.8V

As described in the Enable and Disable Guidelines section, it is generally recommended that VEXT,B> VEXT,A +

0.8V; however, the device can still operate in the condition where VEXT,B < VEXT,A + 0.8V as long as additional

considerations are made for the design.

Typical Operation (VEXT,B > VEXT,A + 0.8V): in this scenario, pullup resistors are not required on the A-side for

proper down-translation. When down translating from B to A, the A-side I/O ports will clamp at VEXT,A to provide

proper voltage translation. For further explanation of device operation, see the Down Translation with the LSF

Family video.

Requirements for VEXT,B < VEXT,A + 0.8V Operation: in this scenario, there is not a large enough voltage

difference between VEXT,A and VEXT,B so that the A side I/O ports will be clamped at VEXT,A, but rather at a

voltage approximately equal to VEXT,B – 0.8V. For example, if VEXT,B = 1.8V and VEXT,A = 1.2V, the A-side I/Os

will clamp to a voltage around 1.0V. Therefore, to operate in such a condition, the following additional design

considerations must be met:

• VEXT,B must be greater than VEXT,A during operation (VEXT,B > VEXT,A)

• Pullup resistors should be populated on A-side I/O ports for the line to be fully pulled up to the desired

voltage.

Figure 8-4 shows an example of this setup, where 1.2V ↔ 1.8V translation is achieved with the LSF0002. This

type of setup also applies for other voltage nodes such as 1.8V ↔ 2.5V, 1.05V ↔ 1.5V, and others as long as the

Recommended Operating Conditions table is followed.

LSF0002

SDLS975 – APRIL 2024

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