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STMPE1601 数据表(PDF) 28 Page - STMicroelectronics

部件名 STMPE1601
功能描述  16-bit enhanced port expander with keypad and PWM controller Xpander Logic
PDF  58 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STMPE1601 数据表(HTML) 28 Page - STMicroelectronics

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Interrupt system
STMPE1601
28/58
9.2
Programming sequence
To configure and initialize the Interrupt Controller to allow interruption to host, observe the
following steps:
●
Set the INT_EN_MASK and INT_EN_GPIO_MASK registers to the desired values to
enable the interrupt sources that are to be expected to receive from.
●
Configure the output interrupt type and polarity and enable the global interrupt mask by
writing to the INT_CTRL.
●
Wait for interrupt.
●
Upon receiving an interrupt, the INT pin is asserted.
●
The host comes to read the INT_STA register through the I2C interface. A ‘1’ in the
INT_STA bits indicates that the corresponding interrupt source is triggered.
●
If the IS8 bit in INT_STA register is set, the interrupt is coming from the GPIO controller.
Then, a subsequent read is performed on the INT_STA_GPIO register to obtain the
interrupt status of all 16 GPIOs to locate the GPIO that triggers the interrupt. This is a
feature so-called ‘Hot Key’.
●
After obtaining the interrupt source that triggers the interrupt, the host performs the
necessary processing and operations related to the interrupt source.
●
If the interrupt source is from the GPIO Controller, two write operations with value of ‘1’
are performed to the ISG[x] bit (INT_STA_GPIO) and the IS[8] (ISR) to clear the
corresponding GPIO interrupt.
●
If the interrupt source is from other module, a write operation with value of ‘1’ is
performed to the IS[x] (ISR) to clear the corresponding interrupt.
●
Once the interrupt is being cleared, the INT pin will also be de-asserted if the interrupt
type is level interrupt. An edge interrupt will only assert a pulse width of 250ns.
●
When the interrupt is no longer required, the IC0 bit in INT_CTRL may be set to ‘0’ to
disable the global interrupt mask bit.



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