ADC3421 datasheet(49/80 Pages) TI2

49 / 80 page

SDOUT

SCLK

SD_DELAY

R/W

A13

A12

A11

SDATA

SCLK

SEN

SDOUT

= 1

ADC3421, ADC3422, ADC3423, ADC3424

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SBAS673A – JULY 2014 – REVISED OCTOBER 2015

9.5.1.1.2

Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.

This readback mode may be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:

1. Drive the SEN pin low.

2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.

3. Set bit A14 in the address field to 1.

4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.

5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.

6. The external controller can latch the contents at the SCLK rising edge.

7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the

SDOUT pin must float. Figure 144 shows a timing diagram of the serial register read operation. Data appear on

the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 145.

Figure 144. Serial Register Read Timing Diagram

Figure 145. SDOUT Timing Diagram

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