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MB85AS12MT 数据表(PDF) 8 Page - RAMXEED LIMITED

部件名 MB85AS12MT
功能描述  12M (1536 K X 8) Bit SPI
PDF  27 Pages
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制造商  RAMXEED [RAMXEED LIMITED]
网页  https://www.ramxeed.com/
标志 RAMXEED - RAMXEED LIMITED

MB85AS12MT 数据表(HTML) 8 Page - RAMXEED LIMITED

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MB85AS12MT
8
DS501-00071-1v1-E
READ
The READ command reads ReRAM memory cell array data. Arbitrary 24 bits address and op-code of READ
are input to SI. The 3-bit upper address bit is invalid. And in case of designating address other than effective
region (180000H to 1FFFFFH), the command itself is ignored. Then, 8-cycle clock is input to SCK. SO is
output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen,
the READ command is completed, but keeps on reading with automatic address increment which is enabled
by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most
significant address (17FFFFH), it rolls over to the starting address, and reading cycle keeps on infinitely.
WRITE
The WRITE command writes data to ReRAM memory cell array. WRITE op-code, arbitrary 24 bits of address
and 8 bits of writing data are input to SI. The 3-bit upper address bit is invalid. And in case of designating
address other than effective region (180000H to 1FFFFFH), the command itself is ignored. During the CS is
low, input writing data are temporary saved in the data register. The maximum writing data size is 256 bytes
during this CS = low period. If the input writing data are more than 8 bits, it is possible to continue writing
with automatic address increment. When it reaches the most significant address, it rolls over to the starting
address, and writing cycle can be continued up to 256 bytes (which is the size of data register). Data exceed
256 bytes can not be written.
After rising edge of CS, MB85AS12MT starts writing operation to nonvolatile memory and set WIP bit in
status register to “1”. After this writing operation has finished, reset this WIP bit from “1” to “0”. Although the
RDSR command is executable for WIP polling during this writing process, any other commands will not be
performed.
CS
SCK
SI
Invalid
MSB
LSB
MSB
Data Out
LSB
High-Z
Invalid
45
0123
26 27
6 7 8 9 10 11 12 13 14 15
38 39
28 29 30 31 32 33 34 35 36 37
00000011 X
32
X X 20 19 18 17 16
54
SO
76
3
10
54
210
CS
SCK
Data In
SI
MSB
LSB
MSB
LSB
High-Z
10 11
0123456789
14 15
26
31 32
12 13
27 28 29 30
33 34 35 36 37 38 39
0000001
3
0 X X X 20 19
2
1
0
SO
18 17 16
5
4
3
2
1
0
7654



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