AMC7832IPAP datasheet(39/74 Pages) TI2

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A14

R/W

SCLK

SDI

SDO

A13

A12

A11

A10

A14

R/W

SCLK

SDI

SDO

A13

A12

Addr N

Addr N +1 (ascending )

Addr N -1 (descending )

AMC7832

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SLAS836 – MARCH 2014

8.4 Programming

The AMC7832 is controlled through a flexible four-wire serial interface that is compatible with SPI type interfaces

used on many microcontrollers and DSP controllers. The interface provides read/write access to all registers of

the AMC7832.

Each serial interface access cycle is exactly (N+2) bytes long, where N is the number of data bytes. A frame is

initiated by asserting CS low. The frame ends when CS is deasserted high. In MSB first mode, the first bit

transferred is the R/W bit. The next 15 bits are the register address (32768 addressable registers), and the

remaining bits are data. For all writes, data is committed in bytes as the 8th data bit of a data field is clocked in

on the rising edge of SCLK. If the write access is not a multiple of 8 clocks, the trailing data bits will not be

committed. On read access, data is clocked out on the falling edge of SCLK on the SDO terminal.

The figures below show the access protocol used by the interface. Data is by default accepted as MSB (Most

Significant Bit) first but the AMC7832 can be configured to accept LSB (Least Significant Bit) first operations as

long as the LSB_Order bit in the Interface Configuration 0 register (address 0x00) is set accordingly.

Figure 53. Serial Interface Write Bus Cycle

Figure 54. Serial Interface Read Bus Cycle

For operations that require large amounts of data to be passed to or from the AMC7832, streaming mode is

supported. In streaming mode multiple bytes of data can be written to or read from the AMC7832 without

specifically providing instructions for each byte and is implemented by continually holding the CS active and

continuing to shift new data in or old data out of the device.

The instruction phase includes the starting address. The AMC7832 starts reading or writing data to this address

and continues as long as CS is asserted and single byte writes has not been enabled in the Interface

Configuration 1 register (address 0x01). The AMC7832 automatically increments or decrements the address

depending on the setting of the address ascension bit in the Interface Configuration 0 register (address 0x00).

If the address is decrementing and 0x0000 is reached, the next address used is address 0x7FFF. If the address

is incrementing and address 0x7FFF is reached, the next address used is 0x0000. Care should be taken when

writing to 0x0000 and 0x0001 as writing to these addresses may change the configuration of the serial interface.

Therefore it is advised that 0x0001 be the first address written and that streaming stops prior to reaching this

address.

The figures below show the access protocol used in streaming mode.

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AMC7832IPAP 数据表(PDF) 39 Page - Texas Instruments

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