AMC7836IPAPR datasheet(29/91 Pages) TI2

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AMC7836

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SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018

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7.3.1.2 DAC Register Structure

The input data of the DACs is written to the individual DAC data registers (address 0x50 through 0x6F) in straight

binary format for all output ranges (see Table 2).

Table 2. DAC Data Format

DIGITAL CODE

DAC OUTPUT VOLTAGE (V)

0 to 5 V RANGE

0 to 10 V RANGE

–5 to 0 V RANGE

–10 to 0 V RANGE

0000 0000 0000

–5

–10

0000 0000 0001

0.00122

0.00244

–4.99878

–9.99756

1000 0000 0000

2.5

–2.5

–5

1111 1111 1110

4.99756

9.99512

–0.00244

–0.00488

1111 1111 1111

4.99878

9.99756

–0.00122

–0.00244

Data written to the DAC data registers is initially stored in the DAC buffer registers. The transfer of data from the

DAC buffer registers to the active registers is initiated by an update command in the register update register

(address 0x0F). When the active registers are updated, the DAC outputs change to the new values.

The host has the option to read from either the buffer registers or the active registers when accessing the DAC

data registers. The DAC read back option is configured by the READBACK bit in the interface configuration 1

7.3.1.3 DAC Clear Operation

Each DAC can be set to a CLEAR state using either hardware or software. When a DAC goes to CLEAR state, it

is loaded with a zero-code input and the output voltage is set according to the auto-range detector output range.

The DAC buffer or active registers do not change when the DACs enter the CLEAR state which makes it

possible to return to the same voltage output before the clear event was issued. Even though the contents of the

active register do not change while a DAC is in CLEAR state, a data-register read operation from the active

registers while in this state returns zero-code. This functionality enables the ability to determine the DAC output

voltage regardless of the operating state (CLEAR or NORMAL).

NOTE

The DAC buffer and active registers can be updated while the DACs are in CLEAR state

allowing the DACs to output new values upon return to normal operation. When the DACs

exit the CLEAR state, the DACs are immediately loaded with the data in the DAC active

registers and the output is set back to the corresponding level to restore operation.

The DAC clear registers (address 0xB0 through 0xB1) enable independent control of each DAC CLEAR state

through software. The DACs can also be forced to enter a CLEAR state through hardware using the ALARMIN

pin. See the Programmable Out-of-Range Alarms section for a detailed description of this method.

The ALARMIN-controlled clear mechanism is just a special case of the device capability to force the DACs into

the CLEAR state as a response to an alarm event. To enable this function, the alarm events must first be

enabled as DAC-clear alarm sources in the DAC clear source registers (address 0x1A through 0x1B). The DAC

outputs to be cleared by the selected alarm events must also be specified in the DAC clear enable registers

(address 0x18 through 0x19).

An alarm event sets the corresponding alarm bit in the alarm status registers. In addition all the DACs set to

clear in response to the alarm event in the DAC clear enable registers enter a CLEAR state. Once the alarm bit

is cleared, as long as no other CLEAR-state controlling alarm events have been triggered, the DACs are

reloaded with the contents of the DAC active registers and the outputs update accordingly.

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