AMC7836IPAPR datasheet(79/91 Pages) TI2

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AMC7836

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SLAS986D – NOVEMBER 2014 – REVISED FEBRUARY 2018

Product Folder Links: AMC7836

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In applications where the DAC channels are driving a large capacitive load and the output changes significantly

(a full scale transition, for instance), the output current of the affected channels may drive to the short circuit

current value as described in the specification table (see Table 64) while the capacitive load is being charged.

This temporary increase in output current may inadvertently cause the AVCC or AVSS to collapse, potentially

resulting in a POR event. It is recommended that the power supply solution for AVCC and AVSS be capable of

supplying short circuit current for all DAC channels with capacitive loads simultaneously to ensure proper device

performance.

9.1 Device Reset Options

9.1.1 Power-on-Reset (POR)

The AMC7836 device includes a power-on reset (POR) function. After all supplies have been established, a POR

event is issued. The POR causes all registers to initialize to the default values, and communication with the

device is valid only after a 250 µs power-on reset delay.

The default operation is power-down mode (register 0x02) in which the device is non-operational except for the

communication interface as determined by the power-down registers. Before enabling normal operation, a

hardware reset should be issued.

A power failure on DVDD, AVDD, AVCC or IOVDD has the potential to initiate a power-on-reset event. As long as

DVDD, AVDD, AVCC, and IOVDD remain above the minimum recommended operating conditions a power failure

event will not occur. When any of these supplies drops below the minimum recommended operating condition

the device may or may not imitate a POR. In this case, issuing a hardware reset or proper POR is recommended

to resume proper operation. To ensure a proper POR event, the DVDD supply must fall below 750 mV. If the

DVDD supply falls below 2.7 V a hardware reset or proper POR must be issued.

9.1.2 Hardware Reset

A device hardware reset event is initiated by a minimum 20-ns logic low on the RESET pin. A hardware reset

causes all registers to initialize to the default values and communication with the device is valid only after a 250-

µs reset delay.

9.1.2.1 Software Reset

A software reset event is initiated by setting the SOFT-RESET bit in the interface configuration 0 register (0x00).

A software reset causes all registers, except 0x00 and 0x01, to initialize to the default values and communication

with the device is valid only after a 100-ns delay.

10 Layout

10.1 Layout Guidelines

•

All power supply pins should be bypassed to ground with a low-ESR ceramic bypass capacitor. The typical

recommended bypass capacitor has a value of 10-µF and is ceramic with a X7R or NP0 dielectric.

•

To minimize interaction between the analog and digital return currents, the digital and analog sections should

have separate ground planes that eventually connect at some point.

•

To reduce noise on the internal reference, a 4.7-µF capacitor is recommended between the REF_CMP pin

and ground.

•

A high-quality ceramic type NP0 or X7R capacitor is recommended because of the optimal performance

across temperature very-low dissipation factor of the capacitor.

•

The digital and analog sections should have proper placement with respect to the digital pins and analog pins

of the AMC7836 device (see Figure 122). The separation of analog and digital blocks allows for better design

and practice as it ensures less coupling into neighboring blocks and minimizes the interaction between analog

and digital return currents.

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