Functional description

STA333ML

12/23

DocID13177 Rev 8

4.2

Fault-detect recovery bypass

The on-chip power output block provides feedback to the digital controller using inputs to

the power control block. The fault input is used to indicate a fault condition (either

overcurrent or thermal). When fault is asserted (set to 0), the power control block attempts a

recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power

output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. This

sequence is repeated for as long as the fault exists.

4.3

Zero-detect mute enable

If this function is enabled, the zero-detect circuit examines each processing channel to see if

2048 consecutive zero value samples (regardless of fs) are received. If so, the channel is

muted.

4.4

Fade-in/out feature

The STA333ML has internal fade-in / fade-out feature when powered on or off, or after a

fault condition.

4.5

Oversampling selector

Pin ONSEL (33) is used to configure the PLL to accept 256 * fs or 384 * fs master clock.

Where fs is the I2S LRCKI frequency:

ONSEL = logical 0 gives256 * fs

ONSEL = logical 1 gives 384 * fs.

4.6

Gain selector

Pin GAIN (34) is used to configure the STA333ML gain:

GAIN = logical 0 gives 0 dBFs

GAIN = logical 1 gives24 dBFs.

4.7

Power-down function

Pin PWDN (23) is used to power down the STA333ML:

PWDN = logical 0 sets the power-down mode

PWDN = logical 1 gives normal operation.

If the power stage is switched off, then the PLL is also switched off.

It is possible to use the PWDN function as a mute function.