DocID13177 Rev 8

15/23

STA333ML

Applications

23

5.2

Internal voltage reference

An embedded voltage regulator produces the reference voltages for the DMOS bridge

driver. It requires two 100 nF capacitors to keep the regulator stable. The capacitors should

be place close to the pins.

Figure 9. Reference voltage block diagram

5.3

PLL filter schematic

It is recommended to use the below scheme and values for the PLL loop filter to achieve the

best performances from the device in general application. Please note that the ground of

this filter scheme has to be connected to the ground of the PLL without any resistive path.

Concerning the component values, please take into account that the greater the filter

bandwidth, the less the lock time, but the higher the PLL output jitter.

Figure 10. PLL application schematic

VCC_REG

VSS_REG

VDD_REG

GND_REG

100 nF

100 nF

Regulator

Input

I2S

Driver P

Driver N

level

shifter

interface

GND

VCC

C3

100n

C6

100n

C7

100n

C8

4.7n

R4

2.2K

C9

680p

GND_SUB

FMT

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

GND_DIG

23 PWDN

24 VDD_PLL

25 FILTER_PLL

26 GND_PLL

27 XTI

28 BICLK

29 LRCLK

30 SDI

31 RESET

32 INT_LINE

33 ONSEL

34 GAIN

35 GND_DIG

36 VDD_DIG

U1

INT_LINE

MCLK

BICLK

LRCLK

SDI

+3.3V

+3.3V

OVERSAMPLING_SEL

GAIN_SEL

PWDN

RESET