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L9026 数据表(PDF) 39 Page - STMicroelectronics

部件名 L9026
功能描述  Automotive configurable multi-channel relay driver 2HS 6HS/LS
PDF  60 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L9026 数据表(HTML) 39 Page - STMicroelectronics

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11
SPI
The SPI interface is used to configure the device, control the outputs and read diagnostic and status registers.
11.1
SPI protocol
The SPI (serial peripheral interface) is a full duplex serial out of frame slave interface made of four lines SO, SI,
CLK and NCS. MOSI and MISO are the lines through which the data is transferred.
Considering the out-of-frame protocol implemented, it is important to ignore the first MISO received at the start of
communication because it is meaningless.
The falling edge of NCS defines the start of the SPI frames. L9026 samples the MOSI line (SI) at the rising edge
of CLK while the output data is shifted out on line MISO (SO) at the falling edge of CLK. (CPOL=’0’, CPHA = ‘0’).
End of SPI access is defined by a rising edge of NCS.
L9026 implements feature to guarantee that SPI frame is considered valid when at least 16 bits have been
transferred: in case of transaction with less than 16 bits is received, the frame will be discarded and ERR bit is
asserted in the next SPI frame. An SPI access with frame longer than 16 bits will not be discarded in order to
allow daisy chain operation.
As additional safety feature, the protocol is also equipped with 1 PARITY bit (odd parity) and a 1 bit frame
counter; the frame counter value to be considered at the beginning of a new communication session after a reset
action is "0". In case an incorrect frame counter value is detected, ERR bit is asserted in the next SPI frame. The
detailed structure of MOSI and MISO frames is shown in Section 11.5: SPI frame structure.
The relationship between MOSI and MISO content during SPI communication is shown in Figure 19: the protocol
implements an out-of-frames strategy.
Figure 19. SPI out-of-frame protocol
During the Limp Home the SPI is in read only mode while no SPI access is possible during device Sleep Mode:
eventual frames are ignored and MISO pin remains in high impedance.
L9026
SPI
DS13397 - Rev 9
page 39/60



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