3.2

Output current limitation

Output current limitation is present to protect the regulator and the application from overload condition, such as

short to ground.

Figure 17. Behavior of output current versus regulated voltage VO

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

IO (A)

5 V

3.3 V

VS = 14 V

Ta = 25 ⁰C

3.3

Enable

The L99VR03 is enabled/disabled by the enable input. With the EN pin above VEn_high and the input voltage

above VS_UVLO, the device becomes active with a stable regulated output voltage. With the EN pin below VEn_low

the device is disabled, reducing the quiescent current as low as 800 nA. The embedded hysteresis (VEn_hyst)

avoids an undefined state of the device in case of slow ramp up signals applied to the EN input. It may happen

that the enable pin must be driven by components supplied at a voltage different from the regulator supply

voltage. In this case the EN input pin must be set high only once VS > 1.5 V. A solution to drive the enable pin is

depicted in the Figure 18.

Figure 18. Typical example of enable control

Power supply-

supply line 1

In any case, since the enable input voltage is linked to the maximum DC supply voltage (VS) applied to the

L99VR03 (-0.3 V to 28 V), special care must be adopted in driving the EN pin to avoid exceeding the absolute

maximum rating.

L99VR03

Applicationinformation

DS14803 - Rev 2

page 11/28