List of figures

Figure 1.

Functional block diagram ............................................................. 2

Figure 2.

Pin connection (top view) ............................................................. 3

Figure 3.

Output voltage vs TJ ................................................................ 8

Figure 4.

Output voltage vs VS ................................................................ 8

Figure 5.

Drop voltage vs output current ......................................................... 8

Figure 6.

Current consumption vs output current ................................................... 8

Figure 7.

Current consumption vs input voltage (IO < 1 mA) ............................................ 8

Figure 8.

Current consumption vs input voltage (IO = 150 mA) .......................................... 8

Figure 9.

Current consumption vs input voltage (IO = 300 mA) .......................................... 8

Figure 10.

PSRR .......................................................................... 8

Figure 11.

Output voltage vs enable voltage (VO = 3.3 V) .............................................. 9

Figure 12.

Output voltage vs enable voltage (VO = 5 V)................................................ 9

Figure 13.

VEN_high vs TJ .................................................................... 9

Figure 14.

VEN_low vs TJ ..................................................................... 9

Figure 15.

Application schematic .............................................................. 10

Figure 16.

Stability plane.................................................................... 10

Figure 17.

Behavior of output current versus regulated voltage VO ....................................... 11

Figure 18.

Typical example of enable control ...................................................... 11

Figure 19.

Undervoltage lock out on output voltage.................................................. 12

Figure 20.

Derating curve ................................................................... 13

Figure 21.

VFDFN8 PC board ................................................................ 14

Figure 22.

PWSSO12 PCB 2 layers ............................................................ 15

Figure 23.

PWSSO12 PCB 4 layers ............................................................ 16

Figure 24.

Rthj-amb vs PCB copper area in still air condition - PWSSO12 ................................... 17

Figure 25.

Thermal impedance curves junction to ambient - PWSSO12.................................... 17

Figure 26.

Thermal fitting model of a Vreg - PWSSO12 ............................................... 18

Figure 27.

VFDFN8 (3x2x0.9 mm 8L wettable flanks) package outline .................................... 19

Figure 28.

PWSSO12 (4.9x3.9x1.5 mm exposed pad down) package outline ................................ 21

Figure 29.

VFDFN8 tape and reel shipment ....................................................... 22

Figure 30.

PWSSO12 tape and reel shipment ..................................................... 23

L99VR03

List of figures

DS14803 - Rev 2

page 27/28