L9907 datasheet(10/49 Pages) STMICROELECTRONICS

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Functional description

L9907

10/49

DS11800 Rev 5

Functional description

2.1

Power supply VB, VCC

Voltage present at VB and VCC pins is monitored in order to inhibit driver and/or boost

functionality in case of under/over voltage detection. A VCC over voltage self test is

embedded for safety integrity check: VCC over voltage threshold can be reduced on

purpose to a level that is always triggered with nominal values on VCC rail. The device is

self protected in case of ground disconnections versus both SGNDx pins. SGND1 and

SGND2 pins are internally shorted and connected to substrate: at least one of these pins

must be connected to board ground. In case of AGND loss, a dedicated comparator will lead

to a POR state for logic, where boost regulator and MOSFET drivers are disabled. This fault

doesn't set any SPI error bit. In case of DGND loss the device is automatically disabled:

MOSFET drivers go in tri-state condition and external FETs are kept off using integrate

passive pull down. In case of BGND ground loss the boost regulator cannot work properly:

the effect is an undervoltage on HS and/or LS side gate voltage monitor.

The ground reference for all the voltages and thresholds available in the device is AGND.

The Exposed Pad (EP) is mainly used for thermal dissipation. It should be grounded and

connected together with SGNDx pins.

2.2

Voltage regulator VDD

The internal 3.3 V voltage regulator is used to supply the internal logic and all internal

blocks. For stability reasons a 100 nF capacitor has to be connected to VDD pin. This

regulator is to be intended for IC internal use only. Suggested limits for external capacitor

are min = 100 nF -20% ma x= 220 nF +20%. All tests are performed with a 100 nF capacitor,

unless otherwise specified.

2.3

EN1 and EN2 pins (ENABLE)

To enable the gate driver functionality EN1 and EN2 have to be pulled high. These pins are

by default internally logically ANDed. In case REGOFF_EN bit in CMD4 SPI frame is set to

1 (refer to SPI mapping,Table 23), EN1 and EN2 have different meanings: EN2 stays the

same as a gate driver functionality enabler, while EN1 will also become an enabler for all the

regulators supplying the pre-driver circuitries. In this way, EN1 becomes a safety control pin

that implements an additional switch-off path.

These pins are also used to enable the SPI write to CMD1 and CMD4. These registers

contain gate driver sensitive to failure management bits which just can be written when at

least one of the ENx pins is pulled low (gate driver disabled).

Nevertheless the pins are used as well to reactivate the gate driver in case of device internal

switch off. Therefore a low cycle of at least 3µs has to be applied after fault condition is

removed to one or both of the ENx pins.

On both pins internal pull down currents are implemented.

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