The DALC208SC6 is particularly optimized to

perform surge protection based on the rail to rail

topology.

follow :

for positive surges

for negative surges

threshold voltage)

According to the curve Fig.5 on page 3, we

assume that the value of the dynamic resistance of

the clamping diode is typically rd = 0.7

1.2V.

For an IEC 1000-4-2 surge Level 4 (Contact

Discharge: Vg=8kV, Rg=330

assume that : Ip=Vg/Rg

≈ 24A.

So, we find:

≈ +23V

≈ -18V

Note: the calculations do not take into account

phenomena due to parasitic inductances

APPLICATION EXAMPLE

If we consider that the connections from the pin

two tracks of 10mm long and 0.5mm large; we

assume that the parasitic inductances of these

tracks are about 6nH.

So when an IEC 1000-4-2 surge occurs, due to the

an extra value equal to Lw.dI/dt.

The dI/dt is calculated as: di/dt = Ip/tr

≈ 24 A/ns

The overvoltage due to the parasitic inductances

is: Lw.di/dt = 6 x 24

≈ 144V

By taking into account the effect of these parasitic

inductances due to unsuitable layout, the clamping

voltage will be :

≈ 167V

≈ -162V

We can reduce as much as possible these

phenomena with simple layout optimization.

It’s the reason why some recommendations have

to be followed (see paragraph "How to ensure a

good ESD protection").

TECHNICAL INFORMATION

SURGE PROTECTION

Fig. A1: ESD behavior; parasitic phenomena due to unsuitable layout.

Lw

VI/O

ESD

SURGE

REF1=GND

I/O

REF2=+Vcc

Vf

Lw di

dt

Lw di

dt

Vcl+ = Vcc+Vf+ Lw

di

dt

surge >0

-Vf- Lw

di

dt

surge <0

Vcl- =

t

tr=1ns

Vcc+Vf

Lw di

dt

Vcl+

POSITIVE

SURGE

167V

-Lw

di

dt

t

tr=1ns

-Vf

Vcl-

NEGATIVE

SURGE

-162V

DALC208SC6

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