Table 25. Output data byte 1

MSB

LSB

D23

D22

D21

D20

D19

D18

D17

D16

Table 26. Output data byte 2

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

Table 27. Output data byte 3

MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

6.4

Operating code definition

The SPI interface features four different addressing modes which are listed in Table 28.

Table 28. Operating codes

OC1

OC0

Meaning

0

0

Write operation

0

1

Read operation

1

0

Read and clear status operation

1

1

Read device information

6.5

Write mode

The write mode of the device allows to write the content of the input data byte into the addressed register (see list

of registers in Table 33. RAM memory map). Incoming data are sampled on the rising edge of the serial clock

(SCK), MSB first.

During the same sequence outgoing data are shifted out MSB first on the falling edge of the CSN pin and

subsequent bits on the falling edge of the serial clock (SCK). The first byte corresponds to the Global Status Byte,

second, third and forth bytes to the previous content of the addressed register. Unused bits will be always read as

0.

Figure 10. SPI write operation

0

0

SDI

SDO

CSN

MSB

Address

Command Byte

(8 bits)

Global Status Byte

MSB

LSB

LSB

MSB

MSB

(previous content of register)

Data

(24 bits)

Data

LSB

LSB

GADG1010171330PS

VNF1048F

SPI functional description

DS13084 - Rev 8

page 24/49