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VNF1048F 数据表(PDF) 29 Page - STMicroelectronics |
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VNF1048F 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 49 page ![]() Address Name Access type Content … … … 31h Reserved 32h Reserved 33h Reserved 34h Reserved … … … 3Fh Advanced operation code C A R&C operation to this address causes all clearable status registers to be cleared 6.12 ROM memory map Table 34. ROM memory map Address Name Description Access Content 00h Company code STMicroelectronics company code Read only 00h 01h Device family Product family code Read only 01h 02h Product code 1 First product letter code Read only 55h 03h Product code 2 Second product letter code Read only 52h 04h Product code 3 Third product letter code Read only 05h 05h Product code 4 Fourth product letter code Read only 4Ah 0Ah Silicon version AD silicon version Read only 02h 10h SPI Mode Bit7 = 0, burst read is disabled, SPI data length = 32bit Bit6, DL2 = 0 Bit5, DL1 = 1 Bit4, DL0 = 1 Bit3, SPI8 =0: 8-bit frame option not available Bit2 =0: Parity check is used Bit1, S1=0 Bit0, S0=1 Read only 31h 11h WD Type 1 A WD is implemented Bit7, WD1 =0 Bit6, WD0 =1 WD period 5ms = 10*ms -> WT[5:0] = 0xA Bit5, WT5 = 0 Bit4, WT4 = 0 Bit3, WT3 = 1 Bit2, WT2 = 0 Bit1, WT1 = 1 Bit0, WT0 = 0 Read only 4Ah 13h WD bit pos. 1 Bit7,WB1 = 0 Bit6,WB2 = 1 WBA[5-0], Bit[5-0] = address of the config. register, where the WD bit is located = 03h = 000011b Read only 43h VNF1048F SPI functional description DS13084 - Rev 8 page 29/49 |
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