LP5030 datasheet(21/62 Pages) TI2

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LP5030, LP5036

www.ti.com

SLVSEH1B – SEPTEMBER 2018 – REVISED JANUARY 2019

Product Folder Links: LP5030 LP5036

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Programming (continued)

There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an

eighth bit, which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1

indicates a READ. The second byte selects the register to which the data is written. The third byte contains data

to write to the selected register.

Figure 18. Acknowledge and Not Acknowledge on I2C Bus

8.5.1.4 I2C Slave Addressing

The device slave address is defined by connecting GND or VCC to the ADDR0 and ADDR1 pins. A total of four

independent slave addresses can be realized by combinations when GND or VCC is connected to the ADDR0

and ADDR1 pins (see Table 2 and Table 3).

The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins.

Global writes to the broadcast address can be used for configuring all devices simultaneously. The device

supports global read using a broadcast address; however, the data read is only valid if all devices on the I2C bus

contain the same value in the addressed register.

Table 2. Slave-Address Combinations

ADDR1

ADDR0

SLAVE ADDRESS

INDEPENDENT

BROADCAST

GND

011 0000

001 1100

GND

VCC

011 0001

VCC

GND

011 0010

VCC

011 0011

Table 3. Chip Address

SLAVE ADDRESS

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Independent

ADDR1

ADDR0

1 or 0

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