LP5030 datasheet(7/62 Pages) TI2

7 / 62 page

LP5030, LP5036

www.ti.com

SLVSEH1B – SEPTEMBER 2018 – REVISED JANUARY 2019

Product Folder Links: LP5030 LP5036

Submit Documentation Feedback

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Voltage on EN, IREF, OUTx, SCL, SDA, VCC

–0.3

Voltage on ADDRx

–0.3

VCC+0.3

Voltage on VCAP

–0.3

Continuous power dissipation

Internally limited

Junction temperature, TJ-MAX

–40

125

°C

Storage temperature, Tstg

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1500

V may actually have higher performance.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V

may actually have higher performance.

7.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±4000

Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

±1500

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

MAX

UNIT

Input voltage on VCC

2.7

5.5

Voltage on OUTx

5.5

Voltage on ADDRx, EN, SDA, SCL

5.5

Operating ambient temperature, TA

–40

°C

(1)

For more information about traditional and new thermal metrics, see Semiconductor and ICPackage Thermal Metrics.

7.4 Thermal Information

THERMAL METRIC(1)

LP5030 or LP5036

UNIT

RJV (QFN)

46 PINS

RθJA

Junction-to-ambient thermal resistance

35.7

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

29.1

°C/W

RθJB

Junction-to-board thermal resistance

16.2

°C/W

ψJT

Junction-to-top characterization parameter

0.9

°C/W

ψJB

Junction-to-board characterization parameter

16.2

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

6.3

°C/W

LP5030 数据表(PDF) 7 Page - Texas Instruments

LP5030 数据表(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载

链接网址

LP5030 数据表(PDF) 7 Page - Texas Instruments

LP5030 数据表(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表 下载

链接网址

数据表下载