ASDMPA series

Plastic SMD MEMS Clock Oscillator

Revision: IR

Initial Release 9/2/2025

Page 3

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Parameters

Min.

Typ.

Max.

Units

Notes

Supply Current (Idd)

50

mA

RL = 50Ω

Output Logic Level

VOH

Vdd-1.145

V

RL = 50Ω

VOL

Vdd-1.695

V

Peak to Peak Output Swing (Vpp)

800

mV

Single ended

Rise Time

Tr

200

250

ps

RL=50Ω, 20% to 80%

Fall Time

Tf

250

300

Duty Cycle

48

52

%

Differential

Integrated Phase Jitter (JPH)

0.65

psRMS 12kHz ~ 20MHz, @ 156.25MHz

Period Jitter RMS (JPER)

2.0

ps

10k cycles, @156.25MHz

Period Jitter (JPTP, pk-pk)

20

ps

10k cycles, @156.25MHz

Parameters

Min.

Typ.

Max.

Units

Notes

Supply Current (Idd)

32

mA

RL = 100Ω

Output Offset Voltage (VOS)

1.15

1.25

1.35

V

RL = 100Ω differential

Peak to Peak Output Swing (Vpp)

250

350

450

mV

Single ended

Rise Time

Tr

120

170

220

ps

RL=100Ω, 20% to 80%

Fall Time

Tf

Duty Cycle

48

52

%

Differential

Integrated Phase Jitter (JPH)

0.65

psRMS

12kHz ~ 20MHz, @156.25MHz,

T =-40 ~ +105°C

0.9

2kHz ~ 20MHz, @156.25MHz,

T =-40 ~ +105°C

Phase Jitter (JRMS-CC)

0.025

0.1

psRMS PCIe Gen 6.0, 64 GT/s

Period Jitter RMS (JPER)

2.5

ps

10k cycles, @156.25MHz

Period Jitter (JPTP, pk-pk)

20

10k cycles, @156.25MHz

Period Jitter RMS (JPER)

3.0

T =-40 ~ +105°C, @156.25MHz

Period Jitter (JPTP, pk-pk)

25

T =-40 ~ +105°C, @156.25MHz

Key Electrical Specifications – LVPECL (VDD = 2.5V±10% or 3.3V±10%, T =-40 ~ +105°C)

Key Electrical Specifications – LVDS (VDD = 2.5V±10% or 3.3V±10%, T =-40 ~ +105°C)