ASDMPA series

Plastic SMD MEMS Clock Oscillator

Revision: IR

Initial Release 9/2/2025

Page 4

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Note 6: Jitter limits are established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards

Parameters

Min.

Typ.

Max. Units

Notes

Supply Current (Idd)

40

mA

RL = 50Ω

Output Logic Level

VOH

0.64

V

RL = 50Ω

VOL

0.1

V

Peak to Peak Output Swing (Vpp)

750

mV

Single ended

Rise Time

Tr

200

260

400

ps

RL=50Ω, 20% to 80%

Fall Time

Tf

250

370

500

Duty Cycle

48

52

%

Differential

Integrated Phase Jitter (JPH)

0.617

psRMS

12 kHz to 20 MHz, @100 MHz

T = –40°C to +105°C

0.460

100 kHz to 20 MHz, @100 MHz

T = –40°C to +105°C

0.212

1.875 MHz to 20 MHz, @100 MHz, T

= –40°C to +105°C

Phase Jitter

TJ Note 6

3.42

86

psPP

PCIe Gen 1.1, TJ = DJ +14.069

x RJ (BER 10–12)

JRMS-CCHF Note 6

0.247

3.1

PSRMS PCIe Gen 2.1, 1.5 MHz to

Nyquist

JRMS-CCHF Note 6

0.08

3.0

PSRMS PCIe Gen 2.1, 10 kHz to 1.5 MHz

JRMS-CC

0.107

1.0

PSRMS

PCIe Gen 3.0 Note 6

0.107

0.30

PCIe Gen 4.0, 16 GT/s

0.043

0.12

PCIe Gen 5.0, 32 GT/s

0.054

0.1

PCIe Gen 6.0, 64 GT/s

Period Jitter RMS (JPER)

2

ps

T =-40 ~ +105°C, @100MHz

Period Jitter (JPTP, pk-pk)

16

ps

T =-40 ~ +105°C, @100MHz

Key Electrical Specifications – HCSL (VDD = 2.5V±10% or 3.3V±10%, T =-40 ~ +105°C)