ASDMPA series

Plastic SMD MEMS Clock Oscillator

Revision: IR

Initial Release 9/2/2025

Page 2

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Note 1

: VDD pin should be filtered with 0.1 μF capacitor.

Note 2: tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled.

Note 3: tDA: See the Output Waveforms and the Test Circuits sections for more information.

Note 4: Includes frequency variations due to initial tolerance, temperature and power supply voltage.

Note 5: Per year after first year

Parameters

Min.

Typ.

Max.

Units

Notes

Disable Time (tDA) Note 3

25

ns

Disable Current

2.5

5

µA

Power Down Option

23

mA

OE Option

Tri-state Function

(Standby/Disable)

"1" (VIH≥0.75*Vdd) or Open: Oscillation

"0" (VIL<0.25*Vdd): Hi Z

V

1.5MΩ pull-up

resistor embedded

Aging

-5.0

+5.0

ppm

First year @ 25°C

-1.0

+1.0

Note 5

Parameters

Min.

Typ.

Max.

Units

Notes

Supply Current (Idd)

27

mA

CL= No Load, 100MHz

Output Logic Level

VOH

0.8*Vdd

V

IOH/IOL=±12mA

VOL

0.2*Vdd

V

Rise Time

Tr

1.2

ns

CL=15pF

20% to 80%

Fall Time

Tf

1.1

ns

Duty Cycle

45

55

%

Integrated Phase Jitter (JPH)

0.65

psRMS 12kHz ~ 20MHz @ 100MHz

Period Jitter (JPTP, pk-pk)

25

ps

@100MHz

Cycle-to-Cycle Jitter (JCC, Peak)

22

ps

@100MHz

Key Electrical Specifications - CMOS (VDD = 2.5V±10% or 3.3V±10%, T =-40 ~ +125°C)

Key Electrical Specifications Cont. - CMOS, LVPECL, LVDS, and HCSL