IS66/67WVR4M8ALL/BLL

Integrated Silicon Solution, Inc.- www.issi.com

3

Rev. A2

07/08/2024

GENERAL DESCRIPTION

The IS66/67WVR4M8ALL/BLL are integrated memory device containing 32Mb Pseudo Static Random Access

Memory using a self-refresh DRAM array organized as 4M words by 8 bits.

The device supports SPI (Serial Peripheral Interface) & QPI (Quad Peripheral Interface) protocols, Very Low Signal

Count (6 signal pins; CLK, CE#, and 4 SIOs), Hidden Refresh Operation, and Industrial temperature and

Automotive A2 grade temperature

.

In Read/Write operation, the address advances to next address automatically until CE# goes to HIGH, and wraps

to 1st address after the last address.

In-Band Reset is supported instead of dedicated RESET# pin, and minimum transferred data size is 8bit.

PERFORMANCE SUMMARY

Read / Write Operation

Maximum Clock Rate

104MHz

Maximum Clock to Access Time at 104MHz

7ns

Maximum Current Consumption

Burst Read or Write ( SPI mode, 33MHz)

8mA

Burst Read or Write ( QPI mode, 104MHz)

15mA

Standby (ISB1, 85°C )

3V

200 uA

1.8V

200 uA