L99PM72GXP datasheet(40/129 Pages) STMICROELECTRONICS

40 / 129 page

Detailed description

L99PM72GXP

40/129

DocID024767 Rev 4

pattern must be sent on the bus. With the detection of the wake up pattern an automatic

state transition to ‘PN_TRX_Selective_Sleep’ state is done. WUP flag is set.

In ‘PN_TRX_Selective_Sleep’ the CAN frame detection logic is enabled. If a valid wake up

frame is detected a state transition to TRX_STBY is done, the WUF flag is set and the micro

is powered up. The remote transition request bit is ignored in wake-up frames. Also masking

of the data length code (DLC) bits is not supported.

After expiration of the frame error counter (FEC), a wake up is performed and the selective

wakeup feature is disabled.

The frame-error-counter (FEC) is cleared after each expiration of the time tsilence whenever

the frame detection logic is enabled.

2.9.5

CAN receive only mode

With the CAN_rec_only bit in Control register 4 it is possible to disable the CAN Transmitter

in active mode. In this mode it is possible to listen to the bus but not sending to it. The

Receiver termination network is still activated in this mode.

2.9.6

CAN looping mode

If the CAN_Loop_en bit in Control register 4 is set the TxDC input is mapped directly to the

RxDC pin. This mode can be used in combination with the CAN Receive only mode, to run

diagnosis for the CAN protocol handler of the micro controller.

2.10

Serial Peripheral Interface (ST SPI Standard 3.0)

A 24 bit SPI is used for bi-directional communication with the micro controller.

During active mode, the SPI

•

triggers the watchdog

•

controls the modes and status of all L99PM72GXP modules (incl. input and output

drivers)

•

provides driver output diagnostic

•

provide L99PM72GXP diagnostic (incl. over temperature warning, L99PM72GXP

operation status)

The SPI can be driven by a micro controller with its SPI peripheral running in

following mode: CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and

output data is changed from the high to low transition of CLK.

This device is not limited to micro controller with a built-in SPI. Only three CMOS-compatible

output pins and one input pin are needed to communicate with the device. A fault condition

can be detected by setting CSN to low. If CSN = 0, the DO pin reflects the global error flag

(fault condition) of the device.

Chip Select Not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the

output pin (DO) is in high impedance state. A low signal activates the output driver and a

L99PM72GXP 数据表(PDF) 40 Page - STMicroelectronics

L99PM72GXP 数据表(HTML) 40 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载