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M41ST85W 数据表(PDF) 18 Page - STMicroelectronics |
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M41ST85W 数据表(HTML) 18 Page - STMicroelectronics |
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18 / 43 page ![]() Operating modes M41ST85W 18/43 DocID7531 Rev 12 included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 volts. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the IBAT value of the M41ST85W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT® top of your choice can then be divided by this current to determine the amount of data retention available (see Table on page 40). For a further more detailed review of lifetime calculations, please see application note AN1012. |
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