M41ST85W datasheet(24/43 Pages) STMICROELECTRONICS

24 / 43 page

Clock operation

M41ST85W

24/43

DocID7531 Rev 12

Figure 16. Backup mode alarm waveform

3.5

Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the watchdog

RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,

and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of

the five-bit multiplier value with the resolution. (For example: writing 00001110 in the

watchdog register = 3*1 or 3 seconds).

Note:

The accuracy of the timer is within ± the selected resolution.

If the processor does not reset the timer within the specified period, the M41ST85W sets the

WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset.

The most significant bit of the watchdog register is the watchdog steering bit (WDS). When

set to a '0,' the watchdog will activate the IRQ/FT/OUT pin when timed-out. When WDS is

set to a '1,' the watchdog will output a negative pulse on the RST pin for trec. The watchdog

when the WDS bit is set to a '1.'

Once per month

Once per year

Table 3. Alarm repeat modes

RPT5

RPT4

RPT3

RPT2

RPT1

Alarm setting

AI03920

VCC

IRQ/FT/OUT

VPFD

ABE, AFE Bits in Interrupt Register

AF bit in Flags Register

HIGH-Z

VSO

HIGH-Z

trec

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